US3603982A

US3603982A - Data entry means

Info

Publication number: US3603982A
Application number: US821311A
Authority: US
Inventors: David M Patti
Original assignee: NCR Corp
Current assignee: NCR Voyix Corp; National Cash Register Co
Priority date: 1969-05-02
Filing date: 1969-05-02
Publication date: 1971-09-07
Anticipated expiration: 1988-09-07
Also published as: CA923429A; GB1238428A; JPS5024569B1

Abstract

An electrooptical data entry means which uses reflected light as a means of encoding characters, each of which is represented by a data entry element. For each character, a photosensitive device is also provided, located in alignment with the corresponding data entry element in a lightproof housing. Also located in the housing is a light source which provides light between the data entry elements and the photosensitive devices. A reflective surface is mounted at an angle on each data entry element, and is so oriented with respect to the light source and the individual photosensitive device for that data entry means, that when a selected data entry device is operated, its reflective surface is moved, from a recess in which it is normally located, into a position which causes it to intercept light from the light source and reflect that light onto the photosensitive device corresponding to the selected data entry element. Illumination of the photosensitive device produces a signal which is effective, through a logical encoding network, to produce an output signal representing the character for the operated data entry element. A shift element is effective, through additional circuitry, to produce a selected one of two possible output signal combinations represented by a given data entry element. Interlocks and various control functions are formed electronically.

Description

United States Patent [72] Inventor David M. Patti Dayton, Ohio [21] Appl. No. 821,3" [22] Filed May 2, 1969 [45] Patented Sept. 7, 1971 [73] Assignee The National Cmh Register Company Dayton, Ohio [54] DATA ENTRY MEANS 20 Claims, 8 Drawing Figs.

[52] US. Cl. 340/365, 178/17 C, 235/145 R [51 Int. (I 606i 3/02 [50] Field of Search 340/365, 337; zoo/61.42; 235/145, 146; 178117, 79

[56] References Cited UNITED STATES PATENTS 3,017,463 1] 1962 Dinsmore et a] 178/79 3,253,087 5/1966 McIntosh 178/79 3,495,239 2/1970 Glorioso et al. 340/365 1 Primary Examiner-Robert L. Richardson AuorneysLouis A. Kline and Albert L. Sessler, Jr.

ABSTRACT: An electrooptical data entry means which uses reflected light as a means of encoding characters, each of which is represented by a data entry element. For each character, a photosensitive device is also provided, located in alignment with the corresponding data entry element in a lightproof housing. Also located in the housing is a light source which provides light between the data entry elements and the photosensitive devices. A reflective surface is mounted at an angle on each data entry element, and is so oriented with respect to the light source and the individual photosensitive device for that data entry means, that when a selected data entry device is operated, its reflective surface is moved, from a recess in which it is normally located, into a position which causes it to intercept light from the light source and reflect that light onto the photosensitive device corresponding to the selected data entry element. Illumination of the photosensitive device produces a signal which is effective, through a logical encoding network, to produce an output signal representing the character for the operated data entry element. A shift element is effective, through additional circuitry, to produce a selected one of two possible output signal combinations represented by a given data entry element. interlocks and various control functions are formed electronically.

I AIENIED E 1 v 350 982 I snsguor! V mvcmon DAVID M. PATTI HIS ATTORNEYS FIG. 3

LIGHT SOURCE I SHIFT FUNCTION ADD 8. SUBT. CHANNEL I E DEVCES EPHOTOSENSITIVE DEVICES SHEET 2 III 7 I I20 QEQQ DATA KEYS I 38 MIRRORS I MIRRORS J J50 momssnsmv CIRCUITRY L SIGNAL AMPLIFICATION 8I DETECTION 7O I A I STROBE TIM'NG a ELECTRONIC INTERLOCK CONTROL CONTROL OUTPUT GATING V V CONTROL DATA INVENTOR DAVID M. PATTI WW 4% MM HIS ATTORNEYS PATENTED SEP 7 SHEET 3 [IF 7 FIG. 4

ZOQQO: S

CH. l

94? log 94 I I0 KQ SUBTRACT Q 550 l64g sgeog E iso I66} INVENTOR DAVID M. PATTI HIS ATTORNEYS PATENTEU SEP 7 I97! SHEET '4 OF I mvsmon DAVID M. PATTI BY a HIS ATTORNEYS PATENIEII SEP 7 WI sum 7 0'? 7 FIG. 6

U W MIN .HHH

INPUT SIGNAL PT n2 I cum. ENTRY o/s 224 STROBE o/s 21c DATA OUTPUT GATE I32 DATA OUTPUT F/F I38 DATA OUTPUT F/F I38 STROBE 0/5 230 (REPEAT CYCLE) CYCLE 0/5 240 (REPEAT CYCLE) INVENTOR DAVID M. PATTI ms ATTORNEYS DATA ENTRY MEANS The invention here described was made in the course of or under a contract or subcontract thereunder with the Department of the Air Force.

BACKGROUND OF THE INVENTION This invention relates to an electro-optical data entry means for producing encoded electrical data output signals in response to manually entered information. These data output signals may be used to effect the entry of information into a utilizing device such as, for example, a teleprinter or an electronic data processing system.

A number of systems have been developed for the generation of data signals in response to manually entered information, using electro-optical means. One such system is shown in US. Pat. No. 3,0923 I0, issued June 4, 1963, inventors Werner Flieg et al., in which a system of mechanical blocking of light paths is employed for producing output signals in accordance with manually entered information. In US. Pat. No. 2,651,463, issued Sept. 8, I953, inventors P. H. Allen et al., certain controls of the operation of a calculating machine are exercised by controlling of light beams through mirrors affixed to control keys.

SUMMARY OF THE INVENTION The present invention provides a data entry device which has the desirable characteristics of compactness, lightweight, high reliability, and flexibility in keyboard size, keyboard layout, and the code employed. These are achieved through the use of electro-optical means for converting information into electrical signals, with each input key being a separate and distinct element, capable of performing its data entry function independently of other keys of the data entry device.

In the present device, the various keys comprising the keyboard are mounted in a substantially lightproof housing. A photosensitive element corresponding to each key is mounted in direct alignment with it in a recessed portion of the housing. A light source in the housing provides light through a space in the housing between the keys and the photosensitive elements. A reflective surface is mounted on the stem of each key, and is so oriented with respect to the light source and the individual photosensitive element for that key, that when the key is depressed, its reflective surface is moved into a position which causes it to intercept light from the light source and reflect that light onto the photosensitive element for the respective key.

Illumination of the photosensitive element produces a signal which is effective, through a logical encoding network, to produce an output signal representing the character for the depressed key. Shift keys are effective, through additional circuitry, to condition the data entry device to function in either an upper case or a lower case mode of operation. Interlocks and other keyboard functions are performed electronically.

It is accordingly an object of the present invention to provide electro-optical data entry means capable of producing output data signals and control signals in response to operation of input elements of the data entry means.

A further object is to provide electro-optical data entry means which uses reflected light as a means of encoding data characters.

An additional object is to provide electro-optical data entry means which is compact, lightweight, reliable, and flexible in capacity and encoding capability.

With these and other objects, which will become apparent from the following description, in view, the invention includes certain novel features of construction and combinations of parts, a preferred form or embodiment of which is hereinafter described with reference to the drawings which accompany and form a part of this specification.

In the drawings:

FIG. 1 is a plan view, partially broken away, of the keyboard unit of the present invention.

FIG. 2 is a sectional view, taken on line 2-2 of FIG. 1.

FIG. 3 is a block diagram, showing the overall organization of the novel data entry means of the present invention.

FIG. 4 is a schematic diagram, showing certain representative keys of the keyboard and associated encoding circuitry.

FIGS. 5A, 5B, and 5C, taken together, constitute a schematic diagram of the operating circuitry forming part of the present invention.

FIG. 6 shows a plurality of electrical waveforms associated with specified components of the operating circuitry.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIGS. 1 and 2 of the drawings, a plurality of keys 20 are mounted for vertical shifting movement in a suitable'keyboard arrangement in the upper surface 22 of a housing 24 which is of substantially lightproof construction. Each key 20 includes a key tip 26 and a key stem 28, and is normally biased to a nonoperated position by a spring 30 positioned between a pin 32 in the key stem and a lower keyboard plate 34 secured to the surface 22 by brackets 36. The lower end of the key stem 28 is angled to receive a mirror or other reflecting surface 38. When the keys are in a nonoperated position, the mirrors 38 are positioned within openings 40 in a block 42 secured within the housing 24. Depression of any key 20 shifts its associated mirror 38 downwardly to a position below the block 42.

A second block 44 is positioned below the block 42 a sufficient distance to provide a space for transmission of light therebetween, as shown in FIG. 2. Aligned with each opening 40 in the block 42 is a cylindrical opening 46 in the block 44, with each such space having an upper bore 48 of reduced diameter.

Positioned with each opening 46 is a photosensitive element 50, which may be a photodiode or other suitable device having the characteristic of undergoing a change in electrical properties, such as a change in resistance, when illuminated by light or other suitable radiation. The reduced diameter bore 48 of the opening 46 minimizes the illumination which can fall upon the element 50, except from directly overhead. Also since the area of each mirror 38 is substantially larger than the corresponding bore 48, alignment problems are minimized. The photosensitive elements 50 are supported on a member 52 which is secured to the block 44. If desired, the member 52 may be a printed circuit board to which the electrodes 54 of the photosensitive elements are connected for incorporation into the operating circuitry of the data entry device, as will subsequently be described in detail.

A light source is provided with the housing 24 and consists in the illustrated embodiment of a plurality of individual light sources 56, such as light bulbs or other radiation-emitting elements, positioned along one interior side of the housing 24 by means of a base 58 secured to said side. The light sources 56 are positioned to cast their illumination primarily into the previously described space between the blocks 42 and 44, both of which are cut away at one side to receive the light sources 56.

The housing 24 is shown in FIG. 2 as being broken away below the block 44. If desired, this housing may be made of sufficient volume to accommodate the operating circuitry for performing various decoding, shift and control functions. Alternatively, the electronic circuitry may be separately housed, if desired. An electrical receptacle 60 is provided at one end of the housing, so that all required electrical circuitry can be interfaced to another device or devices through this receptacIe.

The relationship of the keyboard of FIGS. 1 and 2 to the operating circuitry of the data entry means of the present invention is shown generally in the block diagram of FIG. 3. The

same reference characters

20, 38, 50, and 56 as were appliedto the corresponding elements in FIGS. 1 and 2 are applied to blocks in FIG. 3 representing, respectively, the keys 20, the mirrors 38, the photosensitive elements 50, and the light sources 56.

The operating circuitry will subsequently be described in detail, but is generally represented in FIG. 3 in block form. As shown there, the photosensitive elements 50 corresponding to the various data keys of the keyboard are connected to a diode encoding matrix 62 which converts each output signal from a photosensitive element 50 into a signal on one or more of a plurality of code channels. These signals, in turn, are amplified and shaped by signal amplification and detection circuitry represented by the block 64. As will subsequently be described in detail, certain keys of the keyboard, which perform control functions, have their photosensitive elements 50 directly connected to other portions of the operating circuitry of the data entry device, without passing through the diode encoding matrix.

The keyboard is provided with two shift keys to permit certain keys to have both upper andlower case characters of differing significance, thus effectively increasing the capacity of the keyboard. The shift keys are in the group referred to above in which connections are not made through the diode encoding matrix, but rather directly, to other portions of the circuitry. As will subsequently be described, shift function circuitry, represented by the block 66, controls Add" and Subtract" channel circuitry, represented by the block 62, to produce a different combination of channel output signals when a single data key is depressed, depending upon the condition of the shift function circuitry as determined by operation of a shift key.

The output signals from the signal amplification and detection circuitry of block 64 are applied through an electronic interlock, represented by block 70, to output gating circuitry, represented by block 72. The output signals from block 72 may then be applied over terminals 73 in the case of control signals and terminals 74 in the case of data signals to a suitable utilizing device.

The electronic interlock functions to prevent improper keyboard operation and spurious output signals. A timing and control circuit, represented by block 76, cooperates with the electronic interlock circuitry to provide this function. The electronic circuitry also provides a signal to a strobe control circuit, represented by block-78, for generation of a strobe, or timing, signal which may also be applied over a terminal 80 to a utilizing device for clocking purposes.

The operation of the data entry means shown schematically in FIG. 3 will now be described. When any data key of the keyboard is depressed, its mirror 38 deflects light from the light source 56 vertically through the reduced-diameter bore 48 onto its corresponding photosensitive element 50. The change in resistance in this element, caused by its illumination, produces a signal which is applied over certain channels, according to the particular code established by the diode encoding matrix 62, to the signal amplification and detection circuit 64.

In the amplification and detection circuit 64, the signals on the selected channels are amplified and shaped, and a signal on one channel may be added or subtracted in accordance with whether the data entry device is in an upper case or lower case mode of operation, as controlled by the shift keys.

The output signals in the selected channels are then transmitted to the electronic interlock circuitry represented by block 70, where controls are provided to insure that the signals generated by the depression of only one key at a time are provided as outputs from the data entry device of the present invention. The signals on the selected channels from the electronic interlock circuitry 70 are then applied to the output gating circuitry represented by the block 72. As has been previously mentioned, control signals appear on terminals 73 associated with the output gating circuitry 72. Data channel output signals from the output gating circuitry 72 may take either the form of signals appearing for brief intervals on terminals 74 corresponding to the various channels, or of infonnation which is stored in storage devices, such as bistable elements, associated with the various channels, to permit the encoded information to be sampled at any desired time until the next key 20 is depressed to produce a different combination of encoded output signals.

The strobe signal produced by the strobe control circuit 78 and appearing on the terminal 80 may be used for data sampling, as well as for other purposes, if desired.

The operating circuitry of the data entry device generally shown in block form in FIG. 3 is shown in detail in FIGS. 4, 5A, 5B, and 5C.

Included in FIG. 4, in the bracket at the left side of the figure, is a grouping of representative data entry keys 20 of the keyboard, each with its associated photosensitive element 50 and encoding circuitry, said circuitry extending from a terminal to which may be applied a source of negative potential, over'the photosensitive element 50; and one or more encoding conductors, in each of which is connected a diode 94 to prevent sneak" conductive paths. Each encoding conductor is connected to a terminal 96, 98, 100, I02, I04, I06, 108, or 110. correspondingly numbered terminals appear in FIGS. 5A and 58 to denote the connection of the various encoding channels to the signal amplification and detection circuitry. The terminals 96 to in FIG. 4 are labeled according to the channels which they represent. These terminals are employed for convenience in showing the relationship of the circuit elements on the various sheets of the drawings, and would not be necessary in the actual circuitry.

Not all of the data entry keys of a typical keyboard are shown at the left side of FIG. 4. However, it would be obvious to develop code combinations for as many additional keys as would normally be required.

It will be noted that the encoding conductors corresponding to the various channels are labeled accordingly. The manner in which the Add and Subtract channels are used to indicate the upper case or lower case condition with respect to certain of the keys 20 will be subsequently described.

Referring now to FIGS. 5A and 5B, the

terminals

96, 98, 100, 102, 104, and 106 shown in these figures as well as in FIG. 4 are each connected to a circuit for one of the previously described channels. The circuits of

Channels

1, 2, 3, 4, and 6 are identical, while the circuits of Channel 5 and the Add" and Subtract channels differ in certain respects because of the previously mentioned shift function. For the sake of simplicity in the ensuing description, identical elements in all of the various channel circuits are given the same reference characters.

Each of the

terminals

96 and 110 is connected to a point 112 in its respective channel circuit. From the point 112, a first circuit branch extends over a diode I14 to a common 116, which is connected to a base reference potential, shown here as ground. A terminal 118 is also connected to the common 116.

A second circuit branch extends from the point 112 over a resistor 120 to a second common 122 which is connected over a terminal 124 to a positive source of potential.

A third circuit branch extends from the point 112 of the various channels over a series-connected amplifier 126 and an inverter 128. In the case of

Channels

1, 2, 4, and 6, the circuit continues from the inverter I28 over a branching point 130 to one input of an AND gate 132, the other input of which is connected over a conductor 133 to a character entry" one-shot, as will subsequently be described.

The output of each AND gate 132 branches at a point 134, with one branch connected directly to an output terminal 136, while the other branch is connected to the input of a bistable device or flip-flop 138, the output of which is connected to an output terminal 140. A reset input of the flip-flop 138 is connected over a conductor 142 to a reset" one-shot, as will subsequently be described.

In the case of Channel 5, which includes terminal I04, the circuit continues from the inverter 128 to one input of an OR gate 144. The connection to the other input of the OR gate 144 will be subsequently described. The output of the OR gate 144 is connected to one input of an AND gate I46, having a second input, the connection of which will subsequently be described. The output of the AND gate I46 is connected over a point 130 to one input of an AND gate 132, which is identical to the AND gates I32 previously described for Channels l, 2, 3, 4, and 6. From this point on, the Channel 5 circuit is identical to the channel circuitry previously described for the other numbered channels, with an output terminal 136 extending from the branch point 134, and a second output terminal 140 being connected to a flipflop 138.

In the case of the Add" channel, which includes the terminal 108, the circuit continues from the inverter 128 to one input of an AND gate 148, having a second input, the connec tion of which will subsequently be described. The output of the AND gate 148 is connected to the second input of the previously described OR gate 144 in the Channel 5 circuit.

In the case of the Subtract" channel, which includes the terminal 110, the circuit continues from the inverter 128 to one input of a NAND gate 150, having a second input, the connection of which will be subsequently described. The output of the NAND gate 150 is connected to the second input of the previously described AND gate 146 in the Channel 5 circuit.

In the bracket at the right side of FIG. 4 are shown certain additional keys 20, with their corresponding photosensitive elements 50 and associated circuitry. These are special-purpose keys, the photosensitive elements 50 of which are not connected into the diode encoding matrix represented by block 62 of FIG. 3, but instead are connected into the amplification and detection circuitry shown in FIGS. 58 and 5C. For convenience of illustration, the circuit connections between the photosensitive elements 50 on the right of FIG. 4 and the amplification and detection circuitry in F IGS. 5B and 5C are represented by

terminals

152, 154, 156, 158, 160, 162, 164, and 166, but it will be recognized that such terminals would not be necessary in the actual circuitry.

Among the keys shown at the right side of FIG. 4 are two shift keys 20. Each of these keys is associated with a corresponding photosensitive element 50, and each of the two photosensitive elements 50 is included in a parallel branch extending from a terminal 90 to which a negative source of potential is applied, over the element 50 and a diode 168 to a common point 170, from which the circuit extends to the terminal 152. Referring now to FIG. 5B, the circuit extends from the terminal 152 to a common point 112, from which three branches extend in the same manner as previously described for the numbered channel circuits. A first branch extends from the point 112 over a diode 114 to the common 116; a second branch extends from the point 112 over a resistor 120 to the common 122; and a third branch extends from the point 112 over a series-connected amplifier I26 and inverter 128 to an input ofa flip-flop 172.

A first output from the flip-flop 172 is connected over a resistor 174 to the base of an N PN -type transistor 176, having its emitter connected to a base reference potential, shown as ground, while its collector is connected over a lower case shift indication lamp 178 to a terminal 180, to which is applied a source of positive potential.

A second output of the flip-flop 172 has a first path connected over a resistor 182 to the base of an NPN-type transistor 184, having its emitter connected to a base reference potential, shown here as ground, while is collector is connected over an upper case shift indication lamp 186 to a terminal 188, to which is applied a source of positive potential. A second path from the second output of the flip-flop 172 extends to a point 190. From the point 190, a first branch extends to a second input of the AND gate 148, and a second branch extends to the second input of the NAND gate 150. The manner in which operation of a shift key functions through this logic to provide the desired encoding signals will subsequently be described in the explanation of the circuitry.

Also among the keys shown at the right side of FIG. 4'are a Null" key and a Back Space" key, the associated circuitry of each of which extends from terminals 90 (FIG. 4) over photosensitive elements 50 and the terminals 154 and 156 to a point 112 (FIG. SE), from which a first branch extends over a diode 114 to the common 116; a second branch extends from the point 112 over a resistor 120 to the common [22; and a third branch extends from the point 112 over a series-com nected amplifier I26 and inverter 128 and over a point to one input of an AND gate 132.

The other input of the AND gate 132 in each case is connected to the common 133, while the output ofsaid AND gate is connected to a terminal 192 for the circuit for the Null" key 20 and to an output 194 for the circuit for the Back Space key 20. Signals from the output terminals 192 and 194 may be applied to a utilizing device or otherwise employed as desired.

Alsoamong the keys shown at the right side of FIG. 4 are a plurality of additional special function keys labeled in accordance with the function which they control. These keys are associated with circuitry shown terminating in FIG. 4 at the previously mentioned

terminals

158, 160, 162, 164, and 166. The same terminals are shown in FIGS. 58 and 5C connected to the remaining circuitry associated with these keys. Each of the terminals mentioned above is connected to a point 112, and in each instance three branches extend from the point 112, as has been previously described in connection with the other keys. A first branch extends over the diode 114 to the common 116; a second branch extends over a resistor 120 to the common 122; and a third branch extends from the point 112 over an amplifier 126 connected in series with an inverter 128. From the inverter 128, the circuit associated with these keys extends over a point 130 to output terminals numbered 196, 198, 200, 202, and 204, respectively. Signals applied to these output terminals by depression of a corresponding key may be used in a corresponding utilizing device or otherwise employed as desired.

It will be recalled that in the circuitry associated with each of the numbered channels and with each special function key except the shift keys, the circuit from the inverter 128 extends over a point 130 to either a gate 132 or an output terminal. From the point 130, the various branches are connected to inputs of an OR gate 206, shown in FIG. 5B. The output of the OR gate 206 is connected over an inverter 208 to a point 210 (FIG. 5C), over a conductor 212. From the point 210 a first branch extends over a point 214 to the input of an interlock" one-shot 216, the output of which is connected back, over an inverter 218, to the point 210.

A second branch extends from the point 210 to the input of a delay one-shot 220, the output of which is connected to a point 222. From the point 222, a first branch extends to the input of a character entry" one-shot 224, the output of which is connected to the previously described conductor 133.

From the point 222 a second path extends to a first contact 225 of a switch 226. A second contact 228 of the switch 226 is connected to the input of a strobe one-shot 230, the output of which is connnected over a point 232 to an output terminal 234. A second pair of

contacts

236 and 238 of the switch are provided, with the contact 238 being permanently connected to the contact 228, and with the contact 236 being connected to the input of a cycle" one-shot 240. The output of the cycle" one-shot 240 is connected to the point 232. As shown in FIG. 5C, the switch 226 is normally in a position in which the

contacts

224 and 228 are connected, but may be thrown into a position in which the

contacts

224 and 228 are not connected, and in which the

contacts

236 and 238 are connected. The purpose for this arrangement will be subsequently described.

Returning now to the point 214, a further circuit branch extends from that point to the input of a reset" one-shot 242. The output of this one-shot is connected over an amplifier 244 and an inverter 246 to the previously described conductor 142.

Referring now to FIG. 5A, the light sources 56 are shown therein as being connected in parallel between two conductors 248 and 250, with said conductors being connected to terminals 252 and 254, to which appropriate sources of potential can be connected for providing energy to illuminate the light sources 56.

The manner in which the circuitry of FIGS. 4, A, 5B, and 5C functions to produce the desired output signals when various keys of the data entry device are depressed will now be described with the aid of reference to the various waveforms shown in FIG. 6. The relationship of these waveforms to the circuitry may readily be ascertained by reference to the particular components to which they pertain, and which are identified by reference character in the descriptive column to the left of the waveforms in FIG. 6.

In commencing this operating description, it will be assumed that power to the data entry device is on and that no key is depressed. The photosensitive elements 50 associated with the various keys are therefore in a high-resistance state.

It may be noted in passing that the diodes 94, in combination with the channel conductors to which they are connected, make up the diode encoding matrix referred to generally as the block 62 in FIG. 3. These diodes are employed for the purpose of preventing "sneak paths which might otherwise cause the production of spurious information on the output terminals from the device.

It may also be noted in passing that the diodes 114 connected between the point 112 of each channel and the ground conductor 116 are clamping diodes which prevent the input signal to each amplifier 126 from exceeding a certain potential difference with respect to ground. This prevents the full negative voltage from being applied to the amplifiers 126, which may be of integrated circuit form, and which might be When the flip-flops 138 are utilized for the storage ofoutput information, means must be provided at the beginning of the next data entry operation to reset these flip-flops to zero so that the previously stored information is removed therefrom. This is accomplished by the reset" one-shot 242. As may be seen in the waveform ofFIG. 6, the reset" one-shot 242 has a relatively very short-duration positive-going pulse, which is applied over the amplifier 244, the inverter 246, and the conductor 142 to a reset input of each of the flip-flops 138, for resetting all of said flip-flops at the beginning of each data entry operation of the data entry device.

The delay" one-shot 220 serves the purpose of providing time for stabilization of transient conditions in the circuit to take place on the outputs of the various inverters 128 for the respective channels before sampling'of output data can be initiated.

On the fall of the positive-going pulse from the delay" oneshot 220, the character entry" one-shot 224, and the strobe" one-shot 230 are triggered, and positive-going pulses fromthese one-shots are initiated, as may readily be seen by an examination of the respective waveforms in FIG. 6. The

I character entry one-shot 224 has its output connected, as

damaged by excessive voltage. The resistors 120 are provided between the conductor 124 and the point 112 to maintain the amplifiers 126 in a turned-on condition.

When any key 20 is depressed, the corresponding photosensitive element 50 is illuminated by the deflection of light from the light source 56 onto said element by the mirror 38 of the key, as has been previously described. Illumination of the photosensitive element 50 causes its resistance to drop substantially, so that the negative potential applied to the terminal 90 is reflected at the point 112, as shown in the corresponding wavelength of FIG. 6. This negative-going signal is amplified and inverted by the amplifier 126 and the inverter 128 in the channels of each of the terminals 98 to 110 which are connected through the diode encoding matrix to the photosensitive element 50 of the selected key. Since this signal at the point 112 has been inverted, it is shown in FIG. 6 as a positive going signal. This signal is applied to one input of the AND gates 132 of the selected channels, and is also applied over the point 130 to the OR gate 206, which thus produces a positive output signal, which in turn is inverted by the inverter 208 and applied over the conductor 212 to the point 210. From the point 210, the signal is applied simultaneously to the interlock one-shot 216, the delay" one-shot 220, and the reset" one-shot 242, as shown by the corresponding waveforms in FIG. 6.

As may be seen in FIG. 5A, the output from the data output AND gates 132 may be taken either directly at the output terminals 136 which are connected to the points 134, connected in turn to the outputs of the AND gates 132 for the various data output channels, or the output signals for the various channels may be taken from the output terminals 140 which are connected to the outputs of flip-flops 138. Each of these flip-flops 138 is triggered by the output from the corresponding gate 132 which is applied to the input of the flip-flop 138.

Use of the output flip-flops 138 provides the advantage that the output signals on the terminals 140 may be maintained for as long a period as necessary. This is particularly valuable when the capability of repeating characters which have been previously entered into the keyboard is desired. It may be readily seen that characters can be stored in the flip-flops, and repeat signals may then be utilized to read these characters out a desired number of times. The manner in which a repeat pulse can be generated by the data entry device of the present invention will be subsequently described.

has been previously described, over the conductor 133 to the second inputs of the various output gates 132, so that the operation of output signals from these gates must await the application of the character entry" signal on the conductor 133.

The strobe" one-shot 230 provides an output signal on the terminal 234. This terminal is usually connected to a utilizing device, for sampling. purposes, and controls the utilizing device to sample the data signals on the various channels, either at the terminals 136, or at the terminals 140.

If desired, repeated strobe signals may be produced by operation of the switch 226 from the position in which it is shown in FIG. SC to its other position, in which the

contacts

236 and 238 are electrically connected. When the switch has been moved to this alternate position, the "strobe" one-shot 230 and the cycle one-shot 240 are interconnected to trigger each other and provide a repetition of strobef' signals on the terminal 234 until the switch 226 is moved back to its initial position, in which it is shown in FIG. 5C. The strobe" one-shot 230 is selected to have circuit configuration and biasing such that the change in signal level at its input produced by operation of the switch 226 to its alternate position is effective to cause initial triggering of the strobe" one-shot, while the cycle" one-shot causes its subsequent triggering.

As may be seen by an examination of the waveforms of FIG. 6, the interlock one-shot 216 has a much longer pulse dura-' tion than the delay one-shot 220. The output signal from the interlock" one-shot 216' is applied through the amplifier 218 to the input of the delay one-shot 220 and the reset" one-shot 242 at the point 210, which effectively thus applies the output of the interlock one-shot 216 to its own input, thus effectively locking out itself, the delay" one-shot 220, and the reset" one-shot 242, to prevent spurious information from an inadvertently depressed second key from being processed by the circuitry of the data entry device during the period that the interlock" one-shot output signal remains at a positive level. V

The manner in which the shift circuitry of the present invention functions will now be described. Whenever one ofthe two shift keys 20 is depressed, the resulting signal is applied over the terminal 152 and associated circuitry to the input of the upper case-lower case flip-flop 172 (FIG. SE), to change the state of this flip-flop. The signals on the outputs of the flip-flop 172 then change state, and are applied over the

resistors

174 and 182 to change the state of conduction of the

transistors

176 and 184, to thereby cause one of the

lamps

178 and 186 which has previously been illuminated to be extinguished, and to cause the other one of said two lamps to be illuminated. At the same time, the output signal from the flip-flop 172 is applied over the point 190 to the AND gate 148 and to the NAND gate 150. '7

The purpose of the shift circuitry, controlled by the two shift keys 20, is to increase the capacity of the keyboard of the data entry device, while still maintaining the same number of keys, by making all or some of these keys perform a dual function in indicating one of two possible characters, depending upon whether the data entry device is in an upper case or lower case mode of operation. The mode of operation in which the data entry device is at anygivcn time is shown by the two indication lamps I78 and 186. When the lamp I78 is illuminated, the data entry device is in a lower case mode of operation, and when the lamp I86 is illuminated, the data entry device is in an upper case mode of operation. Either of the two shift keys 20 may be operated to change the mode of the data entry device from upper case to lower case and vice versa, with successive operations of the shift keys being operable to change the mode from whichever mode the data entry device was in previously, to the other mode.

It will be noted from the representative keys shown on the left side of F IG. 4 that all of those keys having both upper case and lower case characters have, in addition to terminals connected to certain of the numbered channels, also a terminal either for the Add" channel (terminal 108) or for the Subtract channel (terminal 110). Signals generated by the illumination of photosensitive elements connected to either the Add or Subtract" channels are applied through the logic network shown in FIGS. 5A and SE to the numbered channel 5 to produce possible alterations in the output of that channel, depending upon whether the data entry device is in the upper case or lower case mode. If, for example, a given key has both the channel 5 terminal 104 and the Subtract terminal 110 associated therewith, depression of that key will produce an output signal in channel 5 if the data entry device is operating in the lower case mode, but will not produce an output in channel 5 if the data entry device is operating in the upper case mode, because of the added presence of a signal from the "Subtract" channel. Similarly, if a key having both upper case and lower case characters does not have a tenninal for channel 5 associated therewith, but does have a terminal 108 associated with the Add" channel associated therewith, then, if the key is depressed when the data entry device is operating in lower case mode, no signal will be produced on the channel 5 output terminal. However, if the key is depressed when the data entry device is operating in an upper case mode, an output signal will be produced on the channel 5 output terminal by depression of that key.

Let it now be assumed, for example, that the key shown in FIG. 4 which has the letter M" in the lower case position is depressed when the data entry device is operating in an upper case mode. Through normal functioning of the circuit of FIGS. 4, 5A, 5B, and 5C, positive output signals are produced for channels I, 3, and 4. In addition, a positive signal appears at the output of the inverter 128 of the Add" channel and is applied to one input of the AND gate 148. Since the data entry unit is operating in the upper case mode, the output of the flipflop 172 which is connected to the point I90 is at a positive level, and therefore positive input signals are applied to the associated inputs ofthe AND gate 148 and the NAND gate 150.

The positive signals at both inputs of the AND gate 148 result in a positive output from that gate, which is applied to one input of the OR gate 144 to produce a positive output from that gate, even though the other input to the OR gate 144, from the channel 5 inverter 128, remains negative. The positive output from the OR gate 144 is applied to one input of the AND gate 146.

Since the output of the inverter I28 of the Subtract" channel remains at a negative level, the associated input to the NAND gate 150 remains negative, and there is accordingly a positive-level output signal from the NAND gate I50 which is applied to the second input of the AND gate 146, resulting in a positive output from'that gate, and therefore a positive channel 5 output signal.

If the same key is depressed when the data entry device is operating in a lower case mode, the signal level at point 190 is negative, and therefore the output of the AND gate I48 is negative, as is the output of the OR gate 144. Consequently the output of the AND gate I46 is negative, producing a negative channel 5 output signal.

In a further example, let it be assumed that the key 20 shown in FIG. 4 which has the number "2 in the lower case position is depressed when the data entry device is operating in an upper case mode. Through normal functioning of the circuit of FIGS. 4, 5A, 5B, and 5C, output signals will be produced for

channels

2, 5, and 6. In addition, a positive signal appears at the output of the inverter 128 of the Subtract" channel, and is applied to one input of the NAND gate I50. Since the data entry device is operating in the upper case mode, the output of the flip-flop 172 which is connected to point 190 is at a positive level, and therefore positive input signals are applied to the associated inputs of the AND gate 148 and the NAND gate 150.

Since the signal level at the output of the inverter I28 for the Add" channel is negative, the output of the AND gate 148 is also negative, even though a positive signal has been applied to the other input of said gate from the point 190. The negative output signal from the AND gate I48 is applied to one input of the OR gate 144, to the other input of which a positive signal from the channel 5 inverter 128 is applied, resulting in a positive output signal from the OR gate 144 which is applied to one input of the AND gate I46.

Since both inputs to the NAND gate are positive, this gate produces a negative output signal which is applied to the other input of the AND gate 146, resulting in a negative output from that gate, and consequently a negative channel 5 output signal.

If the same number 2 key is depressed when the data entry device is operating in a lower case mode, the signal level at point is negative, and therefore the output of the AND gate 148 is still negative. This negative signal, combined with the positive signal from the output of the inverter 128 for channel 5, when combined by the OR gate 144, results in a positive output signal from the OR gate which is applied to one input of the AND gate 146.

Since the input to the NAND gate 150 applied from the point 190 is negative, the output from said NAND gate is positive and, when applied to the other input of the AND gate 146, results in a positive output from said gate, and consequently a positive channel 5 output signal.

The four examples given above are believed to illustrate clearly the manner in which the shift circuitry for the data entry device of the present invention functions. It will be seen from the above that the Add" and Subtract channels function to modify the output of channel 5 when the data entry device is in the upper case mode. In the event that additional keyboard capacity is needed, the channel signal modifying logic can be extended to other data channels in addition to channel 5 by paralleling the logic in a manner believed obvious to one skilled in the art. Also only one signal output modifying channel, either an Add" channel or a "Subtract" channel, rather than both Add" and Subtract channels, could be employed, if desired, by using obvious variations in the logic circuitry. Thus, a large number of output signal combinations can be produced if desired, using a given number of input keys and shift circuitry of the type described herein.

With respect to the various control or special function keys 20 shown on the right side of FIG. 4, it is believed that their operation is clear from an examination of FIGS. 58 and 5C of the drawings. It may be noted that the Null and Back Space keys 20 produce pulsed output signals, due to the fact that the outputs of the inverters 128 for these channels are connected to AND gates 132, the other inputs of which are connected to the character entry one-shot 224, to produce the desired pulsed outputs on the terminals I92 and 194 respectively. On the other hand, the special purpose keys associated with the terminals 158, I60, I62, I64, and 166 are connected directly to their corresponding output terminals 196, I98, 200, 202, and 204, without the use of intervening gates, and therefore the signals produced by depression of these keys change strictly in accordance with the condition of the keys, so that the signal on any of these output terminals remains at a negative level until the key is depressed, and then remains at a positive level until the key is released.

What is claimed is:

1. Data entry means comprising, in combination,

a housing member;

a plurality of data entry elements, each representing at least one character, located in said housing and capable of moving between first and second positions;

radiation source means located within said housing member;

a plurality of radiation-sensitive elements, one for each data entry element, located within said housing member;

radiation-reflecting means associated with each data entry element and capable of altering the path of radiation from the radiation source means, said radiation reflecting means for each data entry element being positioned out of the path of radiation from the radiation source means when the data entry means is in said first position, said radiation reflecting means for a selected data element being positioned to intercept a portion of the radiation from said radiation source means and to direct it onto the radiation-sensitive element corresponding to the selected data entry element when said selected data entry element is depressed into said second position; and

encoding means for producing a combination of output signals representing a character selected by causing moving of a selected data entry element from said first position to said second position.

2. The data entry means of claim 1, also including a plurality of memory elements for storing the combination of output signals generated in response to operation of a data entry element.

3. The data entry means of claim 2, also including repeat means cooperating with said memory elements and capable of producing a repetition of the combination of output signals representing a selected character.

4. The data entry means of claim 1, also including means to prevent the generation of spurious output signals resulting from inadvertent operation of a second data entry element immediately following operation of a first data entry element.

5. The data entry means of claim 1, also including character shift means operable for selecting a desired one of two possible characters corresponding to a single data entry element, and

shift logic means for producing a combination of output signals representing a selected character in accordance with the selection of a corresponding data entry element and the condition of the character shift means.

6. The data entry means of claim in which indicating means are provided to indicate the condition of the shift means. 7

7. The data entry means of claim 5 in which the character shift means are manually operable.

8. The data entry means of claim 1 in which the data entry elements are manually operable.

9. The data entry means of claim 1 in which the radiation reflecting means are mirrors secured to the lower portion of the data entry elements. 7

10. The data entry means of claim I in which the radiationsensitive elements are positioned in line with, but separated from, the corresponding data entry elements, so that radiation from the radiation source means passes between a given data entry element and its corresponding radiation-sensitive element when the data entry element is in said first position, a portion of said radiation being deflected by the radiation reflecting means onto the radiation-sensitive element when the corresponding data entry element is moved into said second position.

11. The data entry means of claim 10 in which the radiation reflecting means are mirrors mounted at an angle to the data entry elements to deflect radiation from said radiation source means onto the radiation-sensitive elements when said data entry elements are moved into said second position.

12. The data entry means of claim 10 in which recesses are provided'within said housing member to receive the radiation reflecting means when the corresponding data entry elements are in said first position.

13. The data entry means of claim 10 in which shielding means is provided within said housing member for each radiation-sensitive element to minimize the impingement thereon of stray radiation. 7

14. The data entry means of claim 10in which the data entry elements are urged by resilient means to said first position.

15. The data entry means of claim 10 in which the data entry elements are provided with key tips for manual operation from said first position to said second position.

16. Data entry means comprising, in combination,

a plurality of data entry elements, each capable of representing an upper case character and a lower case character;

a plurality of data channel circuits, each capable of producing an output code signal;

code signal modifying means;

encoding means for applying signals to selected ones of the data channel circuits and the code signal modifying means in response to operation of the data entry elements, according to a predetermined code; 7

shift means for controlling the data entry means to operate selectively in an upper case mode or a lower case mode; and

circuit means controlled by the shift means and the code signal modifying means for causing a different combination of output code signals to be produced by the data channel circuits in response to operation of a given data entry element when the data entry means is in an-upper case mode of operation than when said data entry means is in a lower case mode of operation.

17. Data entry means comprising, in combination,

a plurality of data entry elements, each capable of representing an upper case character and a lower case character; 7'

a plurality of data channel circuits each capable of producing an output code signal;

an add" channel circuit;

a subtract channel circuit;

encoding means for applying signals to selected ones of the data channel circuits, the add channel circuit, and the subtract" channel circuit in response to operation of the data entry elements, according to a predetermined code;

control circuit means controlled by the shift means, the add" channel circuit, and the subtract" channel circuit for causing a different combination of output code signals to be produced by the data channel circuitsin response to operation of a given data entry element when the data entry means is in an upper case mode of operation than when the data entry means is in a lower case mode of operation.

18. The data entry means of claim 17 in which the shift means includes a bistable element, and in which the control circuit means includes a NAND gate having one input connected to the subtract" channel circuit and one input connected to one output of the bistable element, a first AND gate having one input connected to said one output of the bistable element and one input connected to the add channel circuit, an OR gate having one input connected to one of the data channel circuits and one input connected to the output of the first AND gate, and a second AND gate having one input connected to the output of the OR gate and one input connected to the output of the NAND gate, the output of the second means are connected to first and second outputs of the bistable element to indicate whether the data entry means is in the upper case or lower case mode of operation.

20. The data entry means of claim 18 in which the bistable element is a flip-flop.

Claims

1. Data entry means comprising, in combination, a housing member; a plurality of data entry elements, each representing at least one character, located in said housing and capable of moving between first and second positions; radiation source means located within said housing member; a plurality of radiation-sensitive elements, one for each data entry element, located within said housing member; radiation-reflecting means associated with each data entry element and capable of altering the path of radiation from the radiation source means, said radiation reflecting means for each data entry element being positioned out of the path of radiation from the radiation source means when the data entry means is in said first position, said radiation reflecting means for a selected data element being positioned to intercept a portion of the radiation from said radiation source means and to direct it onto the radiation-sensitive element corresponding to the selected data entry element when said selected data entry element is depressed into said second position; and encoding means for producing a combination of output signals representing a character selected by causing moving of a selected data entry element from said first position to said second position.

5. The data entry means of claim 1, also including character shift means operable for selecting a desired one of two possible characters corresponding to a single data entry element, and shift logic means for producing a combination of output signals representing a selected character in accordance with the selection of a corresponding data entry element and the condition of the character shift means.

6. The data entry means of claim 5 in which indicating means are provided to indicate the condition of the shift means.

9. The data entry means of claim 1 in which the radiation reflecting means are mirrors secured to the lower portion of the data entry elements.

10. The data entry means of claim 1 in which the radiation-sensitive elements are positioned in line with, but separated from, the corresponding data entry elements, so that radiation from the radiation source means passes between a given data entry element and its corresponding radiation-sensitive element when the data entry element is in said first position, a portion of said radiation being deflected by the radiation reflecting means onto the radiation-sensitive element when the corresponding data entry element is moved into said second position.

12. The data entry means of claim 10 in which recesses are provided within said housing member to receive the radiation reflecting means when the corresponding data entry elements are in said first position.

13. The data entry means of claim 10 in which shielding means is provided within said housing member for each radiation-sensitive element to minimize the impingement thereon of stray radiation.

14. The data entry means of claim 10 in which the data entry elements are urged by resilient means to said first position.

16. Data entry means comprising, in combination, a plurality of data entry elements, each capable of representing an upper case character and a lower case character; a plurality of data channel circuits, each capable of producing an output code signal; code signal modifying means; encoding means for applying signals to selected ones of the data channel circuits and the code signal modifying means in response to operation of the data entry elements, according to a predetermined code; shift means for controlling the data entry means to operate selectively in an upper case mode or a lower case mode; and circuit means controlled by the shift means and the code signal modifying means for causing a different combination of output code signals to be produced by the data channel circuits in response to operation of a given data entry element when the data entry means is in an upper case mode of operation than when said data entry means is in a lower case mode of operation.

17. Data entry means comprising, in combination, a plurality of data entry elements, each capable of representing an upper case character and a lower case character; a plurality of data channel circuits each capable of producing an output code signal; an ''''add'''' channel circuit; a ''''subtract'''' channel circuit; encoding means for applying signals to selected ones of the data channel circuits, the ''''add'''' channel circuit, and the ''''subtract'''' channel circuit in response to operation of the data entry elements, according to a predetermined code; shift means for controlling the data entry means to operate selectively in an upper case mode or a lower case mode; and control circuit means controlled by the shift means, the ''''add'''' channel circuit, and the ''''subtract'''' channel circuit for causing a different combination of output code signals to be produced by the data channel circuits in response to operation of a given data entry element when the data entry means is in an upper case mode of operation than when the data entry means is in a lower case mode of operation.

18. The data entry means of claim 17 in which the shift means includes a bistable element, and in which the control circuit means includes a NAND gate having one input connected to the ''''subtract'''' channel circuit and one input connected to one output of the bistable element, a first AND gate having one input connected to said one output of the bistable element and one input connected to the ''''add'''' channel circuit, an OR gate having one input connected to one of the data channel circuits and one input connected to the output of the first AND gate, and a second AND gate having one input connected to the output of the OR gate and one input connected to the output of the NAND gate, the output of the second AND gate producing a normal output signal representative of the signal applied to said one of the data channel circuits when the data entry means is in a lower case mode of operation and producing a different output signal when the data entry means is in an upper case mode of operation.

19. The data entry means of claim 18 in which indicating means are connected to first and second outputs of the bistable element to indicate whether the data entry means is in the upper case or lower case mode of operation.